The present invention relates to a method of fabricating a semiconductor memory device, and more particularly to a method of fabricating a dynamic random access memory device having stacked capacitor memory cell arrays.
Generally, in fabricating a dynamic random access memory device having stacked capacitor memory cell arrays, transistors have been formed before stacked capacitor memory cells are then formed. In order to form the stacked capacitor memory cells, it is necessary to carry out a large number of heat treatments. This means that a large number of heat treatments are carried out after the transistors have already been formed. For example, a reflow process is carried out to planarize an inter-layer insulator to be formed between a gate electrode and a capacitor storage electrode. An impurity diffusion process is carried out to reduce a resistivity of a stacked capacitor electrodes. A thermal oxidation process is further carried out to form a capacitor insulation film. Such heat treatments are generally carried out at a temperature, for example, in the range of 800xc2x0 C. to 950xc2x0 C. An approximate total time of the heat treatments is 120 minutes. Such high temperature heat treatments for a long time period cause impurity diffusions from source/drain diffusion regions whereby the source/drain diffusion regions are made deep and expand in lateral directions. As a result, it becomes likely to cause a reduction of a threshold voltage of the transistor due to short channel effects. In order to avoid this problem with the short channel effects, it is necessary to so design that a channel length defined as a distance between the source and drain regions be not shorter than a critical channel length. A possible reduction in the channel length of the transistor is important for improvement in the switching speed of the transistor. The limitation of the reduction in the channel length of the transistor results in a limitation in improvement in the high speed switching performance of the transistors such as transistors for peripheral circuits, for example, word drivers and timing generators. In order to try to settle the above problems, a technique was proposed for fabricating the dynamic random access memory device having stacked capacitor memory cell arrays. This technique is disclosed in the Japanese laid-open patent publication No. 4-134859. This technique will then be described in detail with reference to FIGS. 1A through 1E which are fragmentary cross sectional elevation views illustrative of a conventional method of fabricating a dynamic random access memory device having stacked capacitor memory cell arrays. The dynamic random access memory device has a memory cell area and a peripheral circuit area including a CMOS circuit. The memory cell array area and an n-channel MOS field effect transistor of the CMOS circuit are illustrated while a p-channel MOS field effect transistor of the CMOS circuit is not illustrated.
With reference to FIG. 1A, a p-well 2 and an n-well 3 are formed over a p-type silicon substrate 1. Over the p-well 2 and the n-well 3, field oxide films 4 are selectively formed by a local oxidation of silicon method. An ion-implantation of impurity is carried out to control a threshold voltage. A gate oxide film 5 is then formed by a thermal oxidation of silicon method. A phosphorus-doped polysilicon film is entirely deposited over the wafer so that the phosphorus-doped polysilicon film extends over the field oxide films 4 and the gate oxide film 5. The phosphorus-doped polysilicon film has a thickness of 300 nanometers. The phosphorus-doped polysilicon film is then patterned to form gate electrodes 6A and 6B. By use of the gate electrodes 6A and 6B and the field oxide films 4 as masks, an ion-implantation of phosphorus is carried out at a dose of 1xc3x971013 cmxe2x88x922 to form phosphorus doped regions. A heat treatment to the substrate is carried out to cause a phosphorus diffusion to thereby form nxe2x88x92-type diffusion layers 7. A first silicon oxide film 8 is then entirely deposited by a chemical vapor deposition method. The first silicon oxide film 8 extends over the field oxide films 4, the gate electrodes 6A and 6B and the nxe2x88x92-type diffusion layers 7. The first silicon oxide film 8 has a thickness of 200 nanometers. The first silicon oxide film 8 is to serve as an inter-layer insulator between MOS transistors and stacked capacitors which will be formed later. The nxe2x88x92-type diffusion layers 7 serve as source/drain diffusion regions of the MOS transistors.
With reference to FIG. 1B, the first silicon oxide film 8 is selectively etched to form stacked capacitor storage electrode contacts 11 over the nxe2x88x92-type diffusion layers 7 adjacent to the field oxide films 4. Other phosphorus-doped polysilicon film is entirely deposited over the wafer so that the other phosphorus-doped polysilicon film is entirely deposited over the wafer so that the other phosphorus-doped polysilicon film extends over the nxe2x88x92-type diffusion layers 7 shown through the stacked capacitor storage electrode contacts 11 and over the first silicon oxide film 8. The other phosphorus-doped polysilicon film has a thickness of 400 nanometers. The phosphorus-doped polysilicon film is then patterned to form stacked capacitor storage electrodes 12 which extends within the stacked capacitor storage electrode contacts 11 to contact with the nxe2x88x92-type diffusion layers 7 shown through the stacked capacitor storage electrode contacts 11 as well as over parts of the first silicon oxide film 8 overlying the gate electrodes 6A. A silicon nitride film is entirely deposited for subsequent oxidation thereof in a steam atmosphere at a temperature of 950xc2x0 C. for 20 minutes to thereby form a stacked capacitor insulation film 13. Still another phosphorus-doped polysilicon film is entirely deposited over the wafer so that the still other phosphorus-doped polysilicon film extends over the stacked capacitor insulation film 13. The still other phosphorus-doped polysilicon film has a thickness of 200 nanometers. A photo-resist 15 is formed over the still other phosphorus-doped polysilicon film. By use of the photo-resist 15 as a mask, the stacked capacitor insulation films 13 and the still other phosphorus-doped polysilicon film are etched to form the stacked capacitor insulation film 13 and stacked capacitor opposite electrode 14. The stacked capacitor insulation films 13 extend over the stacked capacitor storage electrodes 12 and parts of the first silicon oxide film 8 adjacent to the stacked capacitor storage electrodes 12. The stacked capacitor opposite electrodes 14 extend over the stacked capacitor insulation films 13. As a result, the stacked capacitor has been fabricated, which comprises the stacked capacitor storage electrode 12, the stacked capacitor insulation films 13 and the stacked capacitor opposite electrode 14.
With reference to FIG. 1C, by use of the photo-resist 15 as a mask, the first silicon oxide film 8 is then subjected to etch-back to form side wall oxide films 17 on opposite side walls of the gate electrode 6B. Namely, the remaining first silicon oxide films 8 on opposite side walls of the gate electrode 6B serve as the side wall oxide films 17.
With reference to FIG. 1D, the used photo-resist 15 is removed before another photo-resist 16 is selectively formed on a memory cell array area except on a peripheral circuit area. By use of the photo-resist 16, the gate electrode 6B and the side wall oxide films 17 as masks, an ion-implantation of arsenic is carried out at a dose of 3xc3x971015 cmxe2x88x922 to form n+-diffusion layers 18 in the p-well 2 in the peripheral circuit area. As a result, an n-channel MOS field effect transistor having a lightly doped drain structure has been fabricated in the p-well 2 in the peripheral circuit area. The used photo-resist 16 is then removed before another photo-resist not shown is formed which extends over the memory cell area and over the n-channel MOS field effect transistor. By use of the photo-resist not shown, the gate electrode not shown and the side wall oxide films not shown as masks, an ion-implantation of BF2 is carried out at a dose of 3xc3x971015 cmxe2x88x922 to form p-diffusion layers not shown but in the n-well 3 in the peripheral circuit area. As a result, a p-channel MOS field effect transistor having a lightly doped drain structure has been fabricated in the n-well 3 in the peripheral circuit area.
With reference to FIG. 1E, the used photo-resist not shown is removed. A first inter-layer insulator 10 comprising boro-phopho silicate glass film is entirely deposited, which bury the stacked capacitors and the n-channel MOS field effect transistors in the memory cell array area as well as the n-channel and p-channel MOS field effect transistors in the peripheral circuit area. The first inter-layer insulator 10 is then selectively etched to form bit line contacts 20 which are positioned over the nxe2x88x92-type diffusion layers 7 not adjacent to the field oxide films 4 in the memory cell array area as well as over the n+-diffusion layer 18 in the peripheral circuit area and adjacent to the boundary between the memory cell array area and the peripheral circuit area so that the nxe2x88x92-type diffusion layers 7 and the n+-diffusion layer 18 are shown through the bit line contacts 20. A bit line 21 is formed which extends over the first inter-layer insulator 10 and within the bit line contacts 20 so that the bit line 21 is made into contact with the nxe2x88x92-type diffusion layers 7 and the n+-diffusion layer 18 shown through the bit line contacts 20. A second inter-layer insulator 19 comprising boro-phopho silicate glass film is entirely deposited, which extends over the bit line 21 and the first inter-layer insulator 10. The first inter-layer insulator 10 and the second inter-layer insulator 19 are then selectively etched to form a contact hole 23 which is positioned over the n+-diffusion layer 18 in the peripheral circuit area and closer to the n-well 3 so that the n+-diffusion layer 18 in the peripheral circuit area and closer to the n-well 3 is shown through the contact hole 23. An aluminum film is entirely deposited, which extends over the second inter-layer insulator 19 and within the contact hole 23 so that the aluminum film is partially made into contact with the n+-diffusion layer 18 in the peripheral circuit area and closer to the n-well 3. The aluminum film is patterned to form an aluminum interconnection 24 which extends within the contact hole 23 and over the n+-diffusion layer 18 as well as over the second inter-layer insulator 19 but in the vicinity of the contact hole 23. As a result, the dynamic random access memory device having the stacked capacitor memory cell arrays has been fabricated.
The above conventional dynamic random access memory device having the stacked capacitor memory cell arrays has the following problem. In the memory cell array area, the MIS field effect transistors and the stacked capacitors are formed, whilst in the peripheral circuit area the lightly doped drain structure MOS field effect transistors are formed. The inter-layer insulator formed between the MIS field effect transistors and the stacked capacitors comprises the first inter-layer insulator 10 in the memory cell array area. The side wall oxide films 17 are formed from the remaining parts of the first inter-layer insulator 10 in the peripheral circuit area. Namely, the inter-layer insulator formed between the MIS field effect transistors and the stacked capacitors and the side wall oxide films 17 have been formed from the common silicon oxide film as the first inter-layer insulator 10. The side wall oxide films 17 are needed to be the silicon oxide film but may not be available to be reflowed for surface planarization thereof because if the first inter-layer insulator 10 were the boro-phospho silicate glass film and further if the first inter-layer insulator 10 were reflowed for surface planarization thereof, then it is difficult to form desired side wall insulation films at opposite sides of the gate electrode 6B even by use of the etch-back process to the reflowed first inter-layer insulator 10. For this reason, the inter-layer insulator formed between the MIS field effect transistors and the stacked capacitors is not allowed to comprise such boro-phospho silicate glass film and nor permitted to be reflowed for surface planarization thereof. Namely, it is not permitted to carry out the reflow process to the inter-layer insulator formed between the MIS field effect transistors and the stacked capacitors for the purpose of the surface planarization thereof.
Since the surface planarization of the inter-layer insulator to be formed between the MIS field effect transistors and the stacked capacitors, it is extremely difficult to carry out a precise etching to the polysilicon film in order to precisely define the stacked capacitor storage electrodes particularly when advanced dynamic random access memory devices such as 64 M-bits dynamic random access memory devices are designed with 0.35 xcexcm minimum scale. In the 64 M-bits dynamic random access memory devices, word lines or gate electrodes are, for example, designed to be arranged at a distance of approximately 0.4 micrometers, for which reason if the side wall oxide films to be formed at the opposite sides of the gate electrodes are required to have a thickness of 0.1 micrometers, then the first inter-layer insulator is also required to have the same thickness of 0.1 micrometers. A distance between the side wall oxide films of the adjacent gate electrodes provided in the memory cell array area is only 0.2 micrometers as can be understood from the above description with reference to FIG. 1A. In order to form the stacked capacitor storage electrodes, an impurity doped polysilicon film is once deposited entirely not only over the first inter-layer insulator but also within apertures of 0.2 micrometers defined between the side wall oxide films of the adjacent gate electrodes in the memory cell array area. Thereafter, the impurity doped polysilicon film is then selectively etched to form the stacked capacitor storage electrodes. Namely, the polysilicon film deposited within the aperture of 0.2 micrometers defined between the side wall oxide films of the adjacent gate electrodes in the memory cell array area is required to be etched completely as illustrated in FIG. 1B. Actually, however, it is difficult to completely etch the polysilicon film deposited within the aperture of 0.2 micrometers defined between the side wall oxide films of the adjacent gate electrodes in the memory cell array area. When the polysilicon film deposited within the aperture defined between the side wall oxide films of the adjacent gate electrodes in the memory cell array area is not completely etched, a short circuit may be caused between the adjacent stacked capacitor storage electrodes. In order to forcibly carry out the complete removal of the polysilicon film deposited within the aperture of 0.2 micrometers, it is required to carry out an excess etching for a longer etching time, for example, two or three times of the normal etching time during which the polysilicon film on the flat first inter-layer insulator over the gate electrodes has just been removed. Such excess etching causes a slight etching of the side walls of the remaining polysilicon film to be formed as the stacked capacitor storage electrodes. This means it is difficult to obtain the desired definition of the polysilicon film stacked capacitor storage electrodes.
The above conventional dynamic random access memory device having the stacked capacitor memory cell arrays has a further problem to be described below. As described above, the inter-layer insulator formed between the MIS field effect transistors and the stacked capacitors in the memory cell array area and the side wall oxide films 17 comprise the common insulation film, for example, the first inter-layer insulator 10. The first inter-layer insulator 10 to be formed into the side wall oxide films 17 are undesirably etched by the following etching processes. Any spontaneous oxide films having been formed over the nxe2x88x92-type diffusion layers 7 under the stacked capacitor storage electrode contacts 11 are removed by a wet etching with a buffered hydrofluoric acid solution for subsequent deposition of the impurity doped polysilicon film to form the stacked capacitor storage electrodes. At this time, the first inter-layer insulator 10 to be formed into the side wall oxide films 17 are also etched by the buffered hydrofluoric acid solution.
When the impurity doped polysilicon film having been entirely deposited is patterned by etching process to form the stacked capacitor storage electrodes, the first inter-layer insulator 10 to be formed into the side wall oxide films 17 is also undesirably etched.
Any spontaneous oxide films having been formed over the stacked capacitor storage electrodes are removed by a wet etching with the buffered hydrofluoric acid solution for subsequent deposition of the silicon nitride film to form the stacked capacitor insulation films. At this time, the first inter-layer insulator 10 to be formed into the side wall oxide films 17 are also etched by the buffered hydrofluoric acid solution.
When the impurity doped polysilicon film having been entirely deposited is patterned by etching process to form the stacked capacitor opposite electrodes, the first inter-layer insulator 10 to be formed into the side wall oxide films 17 is also undesirably etched.
In each of the above four etching processes, the first inter-layer insulator 10 to be formed into the side wall oxide films 17 is etched by approximately 10-20 nanometers, for which reasons it is difficult to precisely define the side wall oxide films. This means it difficult to obtain desired lightly doped drain structure of the MOS field effect transistors in the peripheral circuit area.
Furthermore, advanced dynamic random access memory devices such as 64 M-bits dynamic random access memory devices may utilize xe2x80x9ccapacitor over bit-line structurexe2x80x9d wherein bit lines are provided under the stacked capacitors because of facilitation of the process of the bit lines and of allowance of a larger plane area of the stacked capacitors. This technique is disclosed by M. Sakao et al. in IEDM""90, 655.
If the fabrication processes described above is applied to the dynamic random access memory devices having such capacitor over bit-line structure, then the stacked capacitors have been formed before the side wall oxide films are formed at the opposite sides of the gate electrode in the peripheral circuit area and the ion-implantation of As and BF2 are sequentially carried out to at high doses to form source/drain diffusion regions of the n-channel and p-channel MOS field effect transistors. The gate electrodes of the MIS field effect transistors is the memory cell array area and the bit lines are formed from a common polysilicon or conductive film. Further, the inter-layer insulator formed between the MIS field effect transistors and the stacked capacitors in the memory cell array area and the side wall oxide films formed at opposite sides of the gate electrode in the peripheral circuit area have been formed from a common insulation film. For the same reasons as described above, it is difficult to carry out the surface planarization of the insulation film. Also for the same reasons as described above, it is difficult to completely etch the polysilicon film deposited within the aperture of 0.2 micrometers defined between the side wall oxide films of the adjacent gate electrodes in the memory cell array area. Furthermore, the insulation film or inter-layer insulator underlying the bit lines remains unetched by the mask of the bit lines.
If, however, in the peripheral circuit area, the MOS field effect transistors have been formed under the bit lines, then it is impossible to form under the bit lines any side wall oxide films of the lightly doped drain structure MOS field effect transistors or source/drain diffusion regions thereof.
In the above circumstances, it had been required to develop a novel method of fabricating a highly advanced dynamic random access memory device having stacked capacitor memory cell arrays so as to allow the required 0.4 micrometers design rule.
Accordingly, it is an object of the present invention to provide a novel method of fabricating a highly advanced dynamic random access memory device having stacked capacitor memory cell arrays formed under bit lines, which is free from any problems as described above.
It is a further object of the present invention to provide a novel method of fabricating a highly advanced dynamic random access memory device having stacked capacitor memory cell arrays formed under bit lines, which is suitable for high integration.
It is a still further object of the present invention to provide a novel method of fabricating a highly advanced dynamic random access memory device having stacked capacitor memory cell arrays formed under bit lines, which is free from a substantial reduction in threshold voltage of MOS field effect transistors formed in a peripheral circuit area and also free from any short channel effects.
It is yet a further object of the present invention to provide a novel method of fabricating a highly advanced dynamic random access memory device having stacked capacitor memory cell arrays formed under bit lines, which allows MOS field effect transistors formed in a peripheral circuit area to show high speed switching performances.
It is a further more object of the present invention to provide a novel method of fabricating a highly advanced dynamic random access memory device having stacked capacitor memory cell arrays formed under bit lines, which allows side wall oxide films to be precisely defined at opposite sides of a gate electrode in a peripheral circuit area.
It is another object of the present invention to provide a novel method of fabricating a highly advanced dynamic random access memory device having stacked capacitor memory cell arrays formed over bit lines, which is free from any problems as described above.
It is further another object of the present invention to provide a novel method of fabricating a highly advanced dynamic random access memory device having stacked capacitor memory cell arrays formed over bit lines, which is suitable for high integration.
It is still another object of the present invention to provide a novel method of fabricating a highly advanced dynamic random access memory device having stacked capacitor memory cell arrays formed over bit lines, which is free from a substantial reduction in threshold voltage of MOS field effect transistors formed in a peripheral circuit area and also free from any short channel effects.
It is yet another object of the present invention to provide a novel method of fabricating a highly advanced dynamic random access memory device having stacked capacitor memory cell arrays formed over bit lines, which allows MOS field effect transistors formed in a peripheral circuit area to show high speed switching performances.
It is still more object of the present invention to provide a novel method of fabricating a highly advanced dynamic random access memory device having stacked capacitor memory cell arrays formed over bit lines, which allows side wall oxide films to be precisely defined at opposite sides of a gate electrode in a peripheral circuit area.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.
The present invention also provides a method of forming stacked capacitors over first field effect transistors having been provided in a memory cell area of a semiconductor memory device and at least a second field effect transistor in a peripheral circuit area of the semiconductor memory device. The method comprises the following steps. A first insulation film is entirely formed which extends over first gate electrodes of the first field effect transistors and within first apertures defined between the first gate electrodes of the first field effect transistors as well as extends over a second gate electrode of the second field effect transistor. A first inter-layer insulator is entirely formed which extends over the first insulation film to completely bury the first and second gate electrodes of the first and second field effect transistors. A surface of the first inter-layer insulator is planarized so that the first inter-layer insulator has a first planarized surface, where the first and second gate electrodes of the first and second field effect transistors are buried in the first inter-layer insulator. At least a first contact hole is selectively formed in the first insulation film extending within the apertures defined between the first gate electrodes to show a surface of one of source and drain regions of the first field effect transistors. A first conductive film is entirely formed which extends over the first planarized surface of the first inter-layer insulator and within the first contact hole so that the first conductive film is made into contact with the one of the source and drain regions of the first field effect transistors. The first conductive film is subjected to a first anisotropic etching to selectively remove part of the first conductive film which extends only over the first planarized surface of the first inter-layer insulator except both in the vicinity of and within the first contact hole to pattern stacked capacitor storage electrodes in the memory cell array area, wherein the first inter-layer insulator protects the first insulation film from the first anisotropic etching. A stacked capacitor insulation film is entirely formed which extends over the stacked capacitor storage electrodes as well as over the first planarized surface of the first inter-layer insulator. A second conductive film is entirely formed which extends over the stacked capacitor insulation film. The second conductive film and the stacked capacitor insulation film are subjected to a second anisotropic etching to selectively remove parts of the second conductive film and the stacked capacitor insulation film from the first planarized surface of the first inter-layer insulator except over and in the vicinity of the first gate electrodes of the first field effect transistors to pattern stacked capacitor insulation films and stacked capacitor opposite electrodes to thereby form stacked capacitors in the memory cell array area, wherein the first inter-layer insulator protects the first insulation film from the second anisotropic etching. Selective removal is made of the first inter-layer insulator extending only in the peripheral circuit area by a wet etching with use of a first photo-resist film provided over the stacked capacitors in the memory cell array area to thereby show the first insulation film only in the peripheral circuit area. Removal is made of the first photo-resist film. The first insulation film only in the peripheral circuit area is subjected to an etch-back by use of a second photo-resist film provided over the stacked capacitors in the memory cell array area so that the first insulation film remains only on opposite side walls of the second gate electrode of the second field effect transistor to thereby form side wall oxide films at the opposite side walls of the second gate electrode.
The present invention also provides a method of forming stacked capacitors over a bit line extending over first field effect transistors having been provided in a memory cell area of a semiconductor memory device and at least a second field effect transistor in a peripheral circuit area of the semiconductor memory device. The method comprises the following steps. A first insulation film is entirely formed which extends over first gate electrodes of the first field effect transistors and within first apertures defined between the first gate electrodes of the first field effect transistors as well as extends over a second gate electrode of the second field effect transistor. A first inter-layer insulator is entirely formed which extends over the first insulation film to completely bury the first and second gate electrodes of the first and second field effect transistors. Planarization is made of a surface of the first inter-layer insulator so that the first inter-layer insulator has a first planarized surface, where the first and second gate electrodes of the first and second field effect transistors are buried in the first inter-layer insulator. Bit line contact holes are selectively formed in the first inter-layer insulator and the first insulation film so as to show surfaces of one of the source and drain regions of each of the first and second field effect transistors. A bit line is selectively formed which extends over the first planarized surface of the first inter-layer insulator and within the bit line contact holes so that the bit line is made into contact with the surfaces of the one of the source and drain regions of each of the first and second field effect transistors. A second inter-layer insulator is entirely formed which extends over the bit line and the first planarized surface of the first inter-layer insulator. Planarization is made of a surface of the second inter-layer insulator so that the second inter-layer insulator has a second planarized surface. At least a first contact hole is formed in the first and second inter-layer insulators and in the first insulation film extending within the apertures defined between the first gate electrodes so as to show a surface of opposite one of the source and drain regions of the first field effect transistors. A first conductive film is entirely formed which extends over the second planarized surface of the second inter-layer insulator and within the first contact hole so that the first conductive film is made into contact with the opposite one of the source and drain regions of the first field effect transistors. The first conductive film is subjected to a first anisotropic etching to selectively remove part of the first conductive film which extends only over the second planarized surface of the second inter-layer insulator except both in the vicinity of and within the first contact hole to pattern stacked capacitor storage electrodes in the memory cell array area, wherein the first and second inter-layer insulators protect the first insulation film from the first anisotropic etching. A stacked capacitor insulation film is formed which extends over the stacked capacitor storage electrodes as well as over the second planarized surface of the second inter-layer insulator. A second conductive film is entirely formed which extends over the stacked capacitor insulation film. The second conductive film and the stacked capacitor insulation film are subjected to a second anisotropic etching to selectively remove parts of the second conductive film and the stacked capacitor insulation film from the second planarized surface of the second inter-layer insulator except over and in the vicinity of the first gate electrodes of the first field effect transistors to pattern stacked capacitor insulation films and stacked capacitor opposite electrodes to thereby form stacked capacitors in the memory cell array area, wherein the first inter-layer insulator protects the first insulation film from the second anisotropic etching. Selective removal is made of the first and second inter-layer insulators extending only in the peripheral circuit area by a wet etching with use of a first photo-resist film provided over the stacked capacitors in the memory cell array area to thereby show the first insulation film only in the peripheral circuit area. Removal is made of the first photo-resist film. The first insulation film only in the peripheral circuit area is subjected to an etch-back by use of a second photo-resist film provided over the stacked capacitors in the memory cell array area so that the first insulation film remains only on opposite side walls of the second gate electrode of the second field effect transistor to thereby form side wall oxide films at the opposite side walls of the second gate electrode.